The present invention generally relates to semiconductor structures and methods of fabricating the same. More particularly, the present invention relates to semiconductor structures having equivalent oxide thickness (EOT) scaled dielectric stacks including high k dielectrics. The present invention also relates to interfacial scavenger techniques that can be employed in fabricating the semiconductor structures having the scaled EOT dielectric stacks.
The reduction of dielectric thickness in a metal oxide semiconductor field effect transistor (MOSFET) is crucial to scaling the gate length and for the progress of semiconductor technology for future generations. With the reduction of the thickness of the conventional oxide/oxynitride dielectric layer in MOSFETs, there is an exponential increase in gate leakage which, in turn, results in an increased power consumption of the device. Moreover, the thickness of the dielectric is now close to a few atomic layers raising reliability concerns. Furthermore, the use of a polysilicon gate electrode has issues with dopant activation and poly depletion that increases the inversion layer thickness.
Gate stacks comprised of a high k gate dielectric, i.e., dielectrics having a dielectric constant that is greater than silicon oxide, and an overlying metal gate are being used to replace conventional gate stacks comprised of silicon oxide and polysilicon to enable transistor scaling. In high k/metal gate stacks there is usually the presence of an interfacial layer (typically silicon dioxide) that exists between the high k dielectric and the underlying semiconductor substrate. In such structures the capacitance of the gate is determined by the following equation:Capacitance of the gate=(capacitance of the high k gate dielectric×capacitance of the interfacial layer)/(capacitance of the high k gate dielectric+capacitance of the interfacial layer)
The interface capacitance limits the overall scalability of the gate stacks and acts as a bottleneck in gate stack scaling. While removal of the interfacial layer is possible, the same results in severe carrier mobility penalty.